1/8 rev. d structure silicon monolithic integrated circuit product name for dsc handshake guard, signal processing and motor drivin g ic model name BH9992GU function ? gyroamp 2ch ? hallamp 2ch ? r-2r type 8bit d/a converter 5ch ? r-2r type 10bit d/a converter 2ch ? no dead zone system pwm driver ? saw wave o scillator ? regulator ? rail to rail amp absolute maximum ratings item symbol standard value unit power supply voltage vc, vdd, pvcc 7.0 v power dissipation *1 pd 1400 mw operation temperature range topr -1070 storage temperature range tstg -40125 h bridge output current1 iout1 300 ma h bridge output current2 *2 iout2 500 ma *1 mounting board specificationrohm standard board materialt he glass fabric base epoxy dimensions50[mm]58[mm]1.75[mm] (8 layers) when using it at ta=25 or more, 14 [mw] of 1[] decreases. *2 instantaneous current1[us] or less operating condition item symbol min. typ. max. unit vc power supply voltage vc 3.0 3.3 5.5 v vdd power supply voltageQvc vdd 2.5 3.0 5.5 v pvcc power supply voltage pvcc 3.0 5.0 5.5 v serial clock frequency fsclk D 1.0 4.0 mhz dacout limit load capacity 1 (dac0out,dac3out,dac4out) cla1 D D 0.1 f between vddout and gnd, load capacity clvddout 1.0 D 30.0 f *3 when vddout is used, the min. operating condition of vc powe r supply voltage is 3.2[v]. ?a radiation is not designed. (*3)
2/8 rev. d physical dimension fig.1 physical dimension (unit mm) lot. no. package type nama vcsp85h4 bh9992 amp9 +in vdd out amp9 -in amp10 -in amp10 +in a 1 2345678 please keep open for the terminal, when you use. +in h amp4 +in amp4 -in g amp2 out amp4 out amp3 out vdd2 amp11 amp3 -in amp3 +in agnd amp11 amp13 -in fgnd1 amp2 -in amp7 amp11 -in out amp13 out out amp1 out amp1 -in evc1 amp7 -in dac4 out amp14 -in vdd1 amp13 +in out out vref1 in amp14 out dac0 d amp9 out amp8 -in c amp10 out xstby vc3 ld data clk amp14 +in dac6 out dac5 dac3 out amp12 -in amp12 out amp8 ? chip backside pin arrangement gnd2 pgnd2 pgnd1 out1f out1r pvcc out2r out2f out vc2 amp12 +in bgnd3
3/8 rev. d pin description pin no. pin name pin explanation pin no. pin name pin explanati on 1-a D D 1-e vddout vdd regulator output 2-a pgnd1 power block ground 2-e vc1 vc power supply 3-a out1f ch1 forward output 3-e amp7-in amp7-input 4-a out1r ch1 reverse output 4-e dac4out dac4 output 5-a pvcc power block power supply 5-e dac0out dac0 output 6-a out2r ch2 reverse output 6-e vref1in amp reference input 7-a out2f ch2 forward output 7-e amp14out amp14 output 8-a D D 8-e amp14-in amp14-input 1-b amp10+in amp10+input 1-f gnd1 gnd 2-b gnd3 gnd 2-f amp2-in amp2-input 3-b vc3 vc power supply 3-f amp7out amp7 output 4-b ld serial data loading input 4-f amp1out amp10 output 5-b data serial data input 5-f amp1-in amp1-input 6-b clk serial clock input 6-f amp11-in amp11-input 7-b gnd2 gnd 7-f vdd1 vdd power supply 8-b pgnd2 power block ground 8-f amp13+in amp13+input 1-c amp10-in amp10-input 1-g amp9+in amp9+input 2-c amp10out amp10 output 2-g amp2out amp2 output 3-c D D 3-g amp4out amp4 output 4-c xstby standby control input 4-g amp3out amp3 output 5-c dac6out dac6 output 5-g vdd2 vdd power supply 6-c dac5out dac5 output 6-g amp11out amp11 output 7-c vc2 vc power supply 7-g amp13out amp13 output 8-c amp12+in amp12+input 8-g amp13-in amp13-input 1-d amp9-in amp9-input 1-h D D 2-d amp9out amp9 output 2-h amp4+in amp4+input 3-d amp8-in amp8-input 3-h amp4-in amp4- input 4-d amp8out amp8 output 4-h amp3-in amp3- input 5-d dac3out dac3 output 5-h amp3+in amp3+ input 6-d amp12-in amp12-input 6-h agnd analog gnd 7-d amp12out amp12 output 7-h amp11+in amp11+input 8-d amp14+in amp14+input 8-h D D
4/8 rev. d whole block diagram fig.2 whole block diagram power driver1 (pvcc) power driver2 (pvcc) pre driver2 vc, pvcc pre driver1 vc, pvcc vdd (vc) pwm1 (vc) pwm2 (vc) dac7ch (vc standard voltage is vdd) clk pgnd data ld gnd2 amp12+in vc2 amp14+in dac5out amp14-in amp12out dac6out amp13+in amp14out vdd1 amp13-in amp12-in amp7out amp7-in amp9+in amp2-in amp8-in gnd1 vc1 amp9-in amp10out amp10-in vc3 amp10+in logic (vc) vref1in hall amp1 (vdd) gyro amp1 (vdd) gyro amp2 (vdd) hall amp2 (vdd) vddout amp9out xstby gnd3
5/8 rev. d electrical characteristic circuit currentvc=3.3[v], vdd =3.0[v], pvcc=5.0[v], dac0out=vr ef1in, ta=25[] except as otherwise noted. item symbol standard value unit notes min. typ. max. current consumption 1 at standby (vc+vdd+pvcc) istby 1.5 10 a xstby, clk, di, ld=l current consumption1 when operating (vc+vdd) icc1 4.0 6.0 ma dac0=080h dac1,2,3,4,5,6=000h current consumption2 when operating (vc+vdd) icc2 11.0 16.5 ma dac0=080h, dac1,2,3,4,=0ffh dac 5,6,=3ffh current consumption3 when operating (pvcc) icc3 25 50 a xstby=h, powstby_n=0 hall sensor input _amp vc=3.3[v], vdd=3.0[v], pvcc=5. 0[v], dac0=080h, dac0out=vref1in , ta=25[] except as otherwise noted item symbol standard value unit notes min. typ. max. output voltage h1vout 2.50 v dac1, 2=0ffh external 500[], 270[] output voltage range (hi) (open loop) h1voh 2.40 v dac1, 2=0ffh outflow current 5.0[ma], output voltage range (low) (open loop) h1vol 0.4 v dac1, 2=000h inflow current 5.0[ma], vin=250[mv] hall sensor output _amp vc=3.3[v], vdd=3.0[v], pvcc=5. 0[v], dac0, dac3, dac4=080h, dac 0out=vref1in, ta=25[] except as otherwise noted item symbol standard value unit notes min. typ. max. output voltage 1 (open loop) h2vout1 2.9 v vinp=1.2[v], vinn=1.1[v] output voltage 2 (open loop) h2vout2 0.2 v vinp=1.1[v], vinn=1.2[v] voltage gain h2gvd 38.5 40.0 41.5 db vin=10[mvpp] (differential voltage input) f=100[hz] cutoff frequency h2fc 4.1 8.1 12. 1 khz -3[db], capa 10[pf] output voltage 1 h3vout1 2.8 v vinp input=1.125, vinn input=0.375 hallsw1,3=on, hallsw2=off dac0=0bfh, dac3,4=040h output voltage 2 h3vout2 0.2 v vinp input=0.375, vinn input=1.125 hallsw1,3=on, hallsw2=off dac0=040h, dac3,4=0bfh output voltage 3 h3vout3 2.8 v vinp input=0.0[v], vinn input=3.0[v] hallsw2=on, hallsw1,3=off dac3,4=0aah output voltage 4 h3vout4 0.2 v vinp input=0.0[v], vinn input=0.0[v] hallsw2=on, hallsw1,3=off dac3,4=055h voltage gain h3gvd -1.5 0 1.5 db vin=10[mvpp] (differential voltage input) f=100[hz] cutoff frequency h3fc 23.0 46.0 69.0 khz -3[db], capa 33[pf]
6/8 rev. d gyro_amp vc=3.3[v], vdd=3.0[v], pvcc=5. 0[v], dac0=080h, dac0out=vref1in , ta=25[] except as otherwise noted item symbol standard value unit notes min. typ. max. output voltage 1 (open loop) g1vout1 2.9 v vinp =1.2[v], vinn =1.1[v] output voltage 2 (open loop) g1vout2 0.2 v vinp =1.1[v], vinn =1.2[v] voltage gain g1gvd 38.5 40.0 41.5 db vin=10[mvpp] (differential voltage input) f=100[hz] cutoff frequency g1fc 4.1 8.1 12. 1 khz -3[db], capa 33[pf] output voltage 1 g2vout1 1.30 1.50 1.70 v gyrosw2=on, gyrosw1, at gyrosw3=off, vinp=open output voltage 2 g2vout2 1.1 1.50 1.90 v gyrosw1, gyrosw2=on, at gyrosw3=off, vinp=open voltage gain g2gvd 36.3 37.8 39.3 db gyrosw2=on, at gyrosw3=off vin=10[mvpp] (differential voltage input) f=100[hz] cutoff frequency g2fc 1.1 2.1 3.1 khz gyrosw2=on, at gyrosw3=off -3[db], capa 100[pf] voltage gain g2gvd2 32.5 34.0 35.5 db gyrosw2=on, at gyrosw3=on vin=10[mvpp] (differential voltage input) f=100[hz] cutoff frequency g2fc2 1.7 3.3 4.9 khz gyrosw2=on, at gyrosw3=on -3[db], capa 100[pf]
7/8 rev. d directions 1absolute maximum ratings this ic might be destroyed when the absolute maximum ratings, s uch as impressed voltages (vc,pvcc,vdd) or the operating temperature range (topr) is exce eded, and whether the destruction is short circuit mode or open circuit mode cannot be specified. pl ease take into consideration the physical countermeasures for safety, such as fusing, if a particular mod e that exceeds the abso lute maximum rating is assumed. 2reverse polarity connection connecting the power line to the ic in reverse polarity (from t hat recommended) will damage the part. please utilize the direction prot ection device as a diode in th e supply line. 3power supply line due to switching and emi noise generated by magnetic components (inductors and motors), using electrolytic and ceramic suppress filter capacitors close to th e ic power input terminals (vcc and gnd) is recommended. please note: the electrolytic capacitor value decr eases at lower temperatures. 4gnd line the ground line is where the lowe st potential and transient vol tages are connected to the ic. 5thermal design do not exceed the power dissipation (pd) of the package specifi cation rating under actual operation, and please design enough temperature margins. (refer to page 10.) 6short circuit mode between terminals and wrong mounting do not mount the ic in the wrong direction and be careful about the reverse-connection of the power connector. moreover, this ic might be destroyed when the dust s hort the terminals between them or gnd. 7radiation strong electromagnetic radiation can cause opera tion failures. 8aso(area of safety operation.) do not exceed the maximum aso and the absolute max imum ratings of the output driver. 9tsd(thermal shut-down) the tsd is activated when the junction temperature (tj) reaches 175 0 c(with +/-25 0 c hysteresis), and the output terminal is switched to hi-z. the tsd circuit aims to in tercept ic from high temperature. the guarantee and protection of ic are not purpose. therefore, plea se do not use this ic after tsd circuit operates, nor use it for assumption that operates the tsd circu it. 10capacitor between output and gnd if a large capacitor is connected between the output and gnd, t his ic might be destroyed when vcc becomes 0v or gnd, because the electric charge accumulated in t he capacitor flows to the output. please set said capacitor to smaller than 0.1f.
8/8 rev. d 11inspection by the set circuit board the stress might hang to ic by connecting the capacitor to the terminal with low impedance. then, please discharge electricity in each and all process. moreover, in the inspection process, please turn off the power before mounting the ic, and turn on after mounting the ic. in a ddition, please take into consideration the countermeasures for electrostatic damage, such as giving the ea rth in assembly process, transportation or preservation. 12each input terminal this ic is a monolithic ic, and has p + isolation and p substrate for the element separation. therefor e, a parasitic pn junction is firmed in this p-layer and n-layer of each element. for instance, the resistor or the transistor is connected to the terminal as shown in the figure below. when the gnd voltage potential is greater than the voltage potential at terminals a or b, the pn junction operates as a parasitic diode. in addition, the parasitic npn tran sistor is formed in said parasi tic diode and the n layer of surrounding elements close to said parasitic diode. these parasitic element s are formed in the ic because of the voltage relation. the parasitic element operating causes the wrong oper ation and destruction. therefore, please be careful so as not to operate the parasitic elements by impressi ng to input terminals lower voltage than gnd(p substrate). please do not apply the voltage to the input terminal when the power-supply voltage is not impressed. moreover, please impress each input terminal low er than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power -supply voltage is impressing. simplified structure of ic 13earth wiring pattern use separate ground lines for control signals and high current power driver outputs. because these high current outputs that flows to the wire impedance changes the gn d voltage for control signal. therefore, each ground terminal of ic must be connected at the one point o n the set circuit board. as for gnd of external parts, it is similar to the above-mentioned. 14reverse brake when you do the reversal brake from the high-velocity revolutio n note the counter electromotive force. moreover, confirm the output current enough and examine the rot ational speed which uses the reversal brake. 15about the capacitor between pvcc-pgnd the pvcc-pgnd capacitor absorbs the change in a steep voltage a nd the current because of the pwm drive. as a result, there is a role to suppress the disorder of the pvcc voltage. h owever, the effect decreases by the influence of the wiring impedance etc. if the capacitor b ecomes far from ic. arrange th e pvcc-pgnd capa citor near ic. 16bypass capacitor between the supply power supplies connect the bypass capacitor( 0.1f) near the pin of this ic. terminal a parasitic element gnd p + p p -substrate gnd p p -substrate cb gnd e e c b gnd resister transistor (npn) p + p + p + terminal a parasitic element terminalb parasitic element terminalb parasitic element surrounding elements
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